Coprocessors and Processor Arrays

With the continuous growth of VLSI technology, it becomes feasible to build large arrays of simple processing elements and functional units in a single chip (e.g. FPGA) to process recurrent algorithms. The approach, however, may be restricted by the limited number of input/output pins that interface the chip and the external memory and peripherals.

Our focus in this area is on the automated synthesis of VLSI arrays of processing elements and functional units, and the automated mapping of recurrent algorithms (e.g. loops) on these VLSI arrays. To cope with the problem of limited I/O, we have studied the use of on-chip memory and mapping algorithms to maximize the reuse of on-chip data. The relevant issues studied include the amount of chip area allocated to on-chip memory, the interconnection topology of processing elements and functional units, their reconfigurability to adapt to applications of different behavior, and the design of compilers to map recurrent algorithms on the system.